Current VLSI Papers and Titles


Image Processing

1. An FPGA Based High Throughput Discrete Kalman Filter Architecture For Real-time Image Denoising.
2. An Efficient Runtime Adaptable Floating-Point Gaussian Filtering Core
3. A Hardware Implementation of Discrete Wavelet Transform for Compression of a Natural Image

Signal Processing

1. ASIC Implementation of Efficient 16-Parallel Fast FIR Algorithm Filter Structure
2. FFT Implementation Using Floating Point Fused Multiplier with Four Term Adder
3. Fir Filter Implementation Using Compressor Based Adder-Tree Structure

Arithmetic Logic

1. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
2. Approximate Ripple Carry and Carry Look ahead Adders –A Comparative Analysis
3. Area and Delay Carry Select Adder Using Brent Kung Architecture
4. Design and Analysis of FPGA Based 32 Bit ALU Using Reversible Gates
5. Low Power High Performance Carry Select Adder
6. Area Efficient Modified Booth Adder based on Sklansky Adder
7. Design of Low Power and Area Efficient Half Adder using Pass Transistor and Comparison of various Performance Parameters


  1. FPGA Implementation of Combined S-Box and InvS-Box of AES
  2. FPGA implementation of Combined AES-128
  3.  FPGA Implementation of Variable Bit Rate OFDM Transceiver System for Wireless Applications

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s